1. Field of the Invention
The present invention relates to a disk array device that manages cache memory, which is accessed by host computers (hereinafter called “host”), by dividing the cache memory into a plurality of cache segments.
2. Description of the Related Art
In some systems (computer systems), a plurality of hosts are connected to one disk array device for sharing storage.
In such a system, the disk array device has a plurality of ports to which a plurality of hosts are usually connected, one for each. A plurality of hosts may also be connected to the same port.
Although data on the storage can be shared in such a system, data may not only be shared but also be built as data dedicated to each host.
Such a system is not only required to provide good performance when a plurality of hosts access the system separately but also expected not to extremely delay responses even when a plurality of hosts access the system at the same time. A plurality of hosts, if connected to one disk array device, results in a hardware resource conflict in the disk array device. This requires the disk array device to appropriately distribute the hardware resources in the device.
One of the important performance factors in a disk array device is cache memory. Although data in a disk array device is all stored on disks, frequently-accessed data is copied to the cache memory. Because data is read from the cache memory much more speedily than data is read from a disk, the average performance of a disk array device depends largely on the cache hit rate.
The LRU (Least Recently Used) control method is a general, efficient cache algorithm for providing a high cache hit rate.
This control method is such that all data in the cache memory is sequentially linked and accessed data is reconnected to the top of the link and, when a cache miss occurs, the data at the end of the link is discarded. According to this control method, if once-accessed data is accessed again immediately after the last access, a cache hit occurs but, if accessed data is not accessed for some time, the data is discarded. Therefore, the more frequently specific data is accessed, the higher the hit rate becomes.
As prior-art technologies, Japanese Patent Laid-Open Publication No. 2001-142778 (pages 6-7, FIG. 1) and Japanese Patent Laid-Open Publication No. 1995-319771 (page 4, FIG. 1) disclose technologies for dividing cache memory into a plurality of segments. However, those prior-art technologies do not disclose the concept of “access group” that will be described nor do they disclose a method for determining cache memory division units used in a disk array device.
When the cache algorithm according to the prior-art LRU control method described above is used, a cache hit cannot be expected to occur if access is made randomly across a range that is larger in relation to the cache size. Although this condition is unavoidable, the problem is that data that has been stored in the cache memory up to that moment is discarded. That is, if an access pattern that is not expected to cause a cache hit and another access pattern that is expected to cause a cache hit are mixed, the access pattern that is expected to cause a cache hit is also affected with the result that the cache hit rate decreases as compared with that when access patterns are not mixed.
This condition is a problem especially in a multi-host environment described at the start of this specification; that is, an environment in which one host makes access to a specific, small area while another host makes access across a wide range. In such a case, although a high cache hit rate is normally expected for the host that makes access to a small area, the cache hit rate is decreased because it is affected by the host that makes access across a wide range.
In particular, when access requests issued from the host that makes access across a wide range discard the cache data while the host that makes access to a small area does not issue access requests, an I/O (Input/Output) request issued from the host that accesses a small area result in a cache miss in most cases.
When this condition is generated, the performance of an application in one host that is expected to cause a cache hit is decreased by the operation of another host and it becomes difficult to estimate the performance of the system. Therefore, a need arises for a method of controlling performance that is less affected by accesses from another host.
A straightforward example is a system where a host that executes backup processing and a host that does not execute business operations but evaluates development performance coexist. A large amount of data is moved during backup processing and normally a cache hit is not expected, and it is desirable that the host that evaluates development performance be expected not to affect the performance of the host that executes business operations. The present invention was made with such an environment in mind.